The present invention relates to a data expansion apparatus for expanding data comprising numeric data and number-of-zeroes data, i.e., data representing the number of successive zeroes.
FIG. 3 shows a prior art data expansion apparatus. Selection means 303 selects either numeric data 301 from an external device or zeroes from zero data device 302. Selection means 311a and 311b each select the output from either read address generator 304 or write address generator 305 and output it to memory means 312a and 312b, respectively. In write operation, i.e., an expansion operation, memory means 312a and 312b store the output of selection means 303 at the addresses specified by the output of write address generator 305 through selection means 311a and 311b, respectively. In read operation, memory means 312a and 312b output the data from the addresses specified by the output of read address generator 304 through selection means 311a and 311b, respectively.
A comparator 309 compares number-of-zeroes data 306 from the external device with the output of counter 307. The output of comparator 309 and a data validation flag 308 are input to controller 3 10, which outputs a control signal to selection means 303, 311a and 311b, read address generator 304, write address generator 305, counter 307, and memory means 312a and 312b. Controller 310 also provides an expansion completion flag 313 to the external device.
The operation of this prior art apparatus is now described. It is assumed that the numeric data and number-of-zeroes data are four bits, and each data block is 8.times.8 bits. The storage capacity of memory means 312a and 312b is one data block each, and the initialization value of counter 307 is zero. The input data for the operation are shown in FIG. 4 and the addresses of each of memory means 312a and 312b are shown in FIG. 5.
In FIG. 3, data validation flag 308 is input to controller 310. Controller 310 then outputs control signals to all circuit blocks to start the data expansion operation. The values of the first set of number-of-zeroes data 306 and numeric data 301 are 0 and 1, respectively. Since the value of the number-of-zeroes data and the initialization value of counter are both zero, comparator 309 immediately outputs a match flag to controller 310.
Selection means 303 selects numeric data 301 of a value 1 and outputs it to memory means 312a in response to the control signal from controller 310. Furthermore, selection means 311a selects address 0 output by write address generator 305 and outputs it to memory means 312a. Thus, numeric data 301 of a value 1 is stored at address 0 of memory means 312a. Controller 310 then outputs an expansion completion flag 313 to the external device and a control signal to counter 307 for initialization. Then, another data validation flag 308 is input to controller 310, and next set of input data are input to the apparatus.
The values of the next set of number-of-zeroes data 306 and numeric data 301 are 7 and 3, respectively, as shown in FIG. 4. Selection means 303 continuously selects and outputs zeroes from zero data device 302 until the value of counter 307 is counted up to 7, matching the value of numeric data 301. Write address generator 305 generates addresses and outputs them to memory means 312a through selection means 311a, counting up in synchronism with counter 307 from address 1. Thus, 0 is stored at addresses 1-7 in memory means 312a. When the output of counter 307 matches the value of number-of-zeroes data 306, comparator 309 sends out a match flag to controller 310.
Selection means 303 selects numeric data 301 of a value 3 and outputs it to memory means 312a in response to the control signal. Furthermore, selection means 311a selects address 8 output by write address generator 305 and outputs it to memory means 312a. Thus, numeric data 301 of a value 3 is stored at address 8 of memory means 312a. Controller 310 then outputs expansion completion flag 313 to the external device and a control signal to counter 307 for initialization. Then, another data validation flag 308 is input to controller 310. Thereafter, the same operation is repeated until the capacity of memory means 312a is full, i.e., until data is written to address 63.
FIG. 6 shows the contents of memory means 312a after the above expansion operation is completed. After memory means 312a completes the expansion operation, it is switched to perform read operation. Controller 310 sends a control signal to initialize write address generator 305 to 0.
FIG. 7 shows the zigzag scan sequence in which the data is read out from memory means 312a. Read address generator 304 generates addresses in this zigzag scan sequence and outputs them to memory means 312a through selection means 311a.
FIG. 8 shows the data read out from memory means 312a in that zigzag manner. In the above apparatus, when memory means 312a is performing read operation, memory means 312b is performing expansion operation. After memory means 312a completes read operation, it is switched to perform expansion operation and memory means 312b is switched to perform read operation. Thus, the expansion operation is performed by alternately switching the operations performed by memory means 312a and 312b.
In the data expansion apparatus described above, the expansion operation for a given data block depends upon the number of continuous zeroes in the data block. The more number of continuous zeroes the data block has, the longer it takes to perform the expansion operation. Moreover, since it is difficult to control the timing of the data transfer to the data expansion apparatus, a buffer or other means is required for storing the data before they are transferred to the expansion apparatus to match the speed of data input and that of expansion operation. Consequently, it results in a larger and more complex device.